The "common-emitter" connection scheme, which has a base-to-emitter input and a collector-to-emitter output, is the most frequently used means of connecting a bipolar transistor into a circuit. This is primarily because the power gain of the common-emitter connection is the highest of the most commonly used connection schemes.
It is often desirable to operate a transistor with sufficient collector-emitter voltage to keep the device in the so-called "non-saturated" region of operation, so that the transistor has current gain between its base-emitter input circuit and its collector-emitter output circuit. If the transistor is biased in this manner, the device can serve as an amplifier or a power-controlling pass device in a regulator. These modes of operation are important and are two of the chief roles for a transistor. If, on the other hand, the transistor is operating in the saturated regime, the device has low gain; as a consequence, the transistor cannot amplify an input signal. It also cannot be used as a power-controlling pass device in a regulator. This is because in order for a regulator to be energy-efficient, the control circuitry driving the pass device must consume less power than is being controlled by the pass device.
An example of a transistor which is designed to operate in the above-described mode is one in a low dropout regulator (LDO), which by definition must be able to provide regulation at low values of the voltage differential between the transistor input and output. This is a desirable feature because the lower the voltage drop across the regulator, the less power "burned" by the regulator, and the higher the efficiency of the overall circuit.
This performance specification imposes certain requirements on the pass transistor used in such regulators. Because the pass device has it collector connected to the output and its emitter connected to the input, the pass device's collector-emitter voltage equals the regulator's input-output voltage; therefore, in order for a LDO regulator to operate at a low input-output voltage differential, the pass device must be able to operate in the non-saturated region at low values of the collector-emitter voltage.
If the collector-emitter voltage of a transistor is small, say, around 1 volt or so (as is often the case for the pass device in an LDO), then the voltage drop due to the collector-emitter resistance may be sufficient to cause the collector voltage at the base-collector interface to be low enough that the base-collector junction is forward biased. This causes the transistor to operate in the saturated region, thereby cutting the current gain (referred to as beta) to a value so low that the base current used to modulate the flow of power out the collector rivals the current being delivered to the load. In such a situation, the transistor is not suitable as a power-controlling device.
This problem provides the motivation for finding ways to reduce the total collector resistance. If successful, this would permit a transistor to be made which operates in the non-saturated region at lower values of the collector-emitter voltage. Such a transistor can be used to make a regulator that operates at a much smaller input-output voltage differential.
FIG. 1 shows a cross-section view of a typical vertical npn bipolar transistor 10. By "vertical" is meant a bipolar transistor having an architecture such that the emitter emits current downward, in a direction perpendicular to the surface of the silicon body of the transistor. Bipolar transistors in which the emitter emits current horizontally, i.e., in a direction parallel to the surface of the silicon body are termed "lateral".
As shown in FIG. 1, bipolar transistor 10 includes a silicon substrate 11 and collector region 19. Below collector region 19 lies a buried layer 14. Collector contact 20 is formed in collector region 19 and over buried layer 14. Base region 12 is formed in collector region 19. Base contact 16 and emitter 18 are formed in base region 12. When transistor 10 is connected in the common-emitter mode, current 15 flows from emitter 18 downward into buried layer 14, laterally along buried layer 14, and upward to collector contact 20.
A typical bipolar transistor manufacturing process, such as one used to manufacture a npn vertical transistor of the type shown in FIG. 1, will now be described. The manufacturing process described is intended for purposes of illustration only, as the present invention is applicable to the layout of any vertical bipolar device, i.e., pnp or npn. In each of the described process steps, the regions of the device which are being operated on are defined by well-known photolithographic techniques used in the semiconductor industry.
In the first step, an n-type dopant is implanted into substrate 11 to form buried layer 14. N-type epitaxial silicon is then grown on top of substrate 11, forming collector region 19. A p-type dopant is then implanted into collector region 19 to form base region 12. This is followed by the implantation of an n-type dopant at a high concentration to form emitter 18 and collector contact 20, and the implantation of a p+ dopant to form base contact 16.
As is well known, and as shown in FIG. 2, the total collector resistance of a bipolar transistor 10 such as that shown in FIG. 1 is equal to the sum of the "down" resistance 30 from emitter 18 to buried layer 14, the resistance 32 of buried layer 14, and the "up" resistance 34 from buried layer 14 to collector contact 20. As previously noted, in order for a LDO regulator to operate at a low input-output voltage differential, the pass device must be able to operate in the non-saturated region at low values of the collector-emitter voltage. This provides the motivation for reducing the total collector resistance, and has stimulated efforts to design bipolar transistor architectures which reduce one or more of the components of the total collector resistance.
The "down" component 30 of the collector resistance can be reduced by enlarging the surface area of the emitter. This spreads out the current flow between the emitter and buried layer, thereby minimizing the voltage drop. An increase in the emitter contact area is usually achieved by arranging multiple emitters in the base region.
The buried layer resistance 32 can be reduced by designing the device so that the current path through the buried layer is broad. This is usually accomplished by increasing the transistor dimension which is perpendicular to the direction of flow of the buried layer current.
The "up" component 34 of the collector resistance can be reduced by increasing the area of the collector contact. This causes the current flowing up to the contact to have a large cross-sectional area so that it encounters little resistance. An increase in the collector contact area is usually achieved by placing additional collector contacts on opposing sides of the base region.
The result of implementing the standard approaches to reducing total collector resistance which are described above is a "conventional" architecture multiple emitter bipolar transistor 100, a top view of which is shown in FIG. 3. Multiple emitter bipolar transistor 100 has a base region 102 which lies over a buried layer 104. Multiple base contacts 106 and emitters 108 are formed in base region 102, typically in alternating parallel stripes. Collector contacts 110 are formed over buried layer 104.
While the conventional architecture shown in FIG. 3 incorporates design features intended to reduce the total collector resistance, it is not the optimal architecture. In particular, the emitter area (and hence its contribution to lowering the down resistance) is limited by the large amount of surface area occupied by the base contacts. If a greater proportion of the base region were covered by emitter instead of base contact, the down resistance component, and hence the total collector resistance, could be reduced even more.
In order to realize a proportionally larger emitter area, designers have modified the conventional layout scheme, and instead used what is termed a "lattice" layout scheme. FIG. 4 shows a top view of a multiple emitter bipolar transistor 200 which is laid out according to the lattice architecture. In the lattice design, a base region 202 again lies over a buried layer 204. As with the architecture of FIG. 3, base contacts 206 and multiple emitters 208 are formed in base region 202, and collector contacts 210 are formed over buried layer 204. However, in this design the emitter area is increased by creating gaps in, or segmenting base contacts 206, and filling the gaps with additional regions of emitter 208. The result is that each base contact 206 is bordered by horizontal 220 and vertical 230 sections of emitter 208. In this design, the total emitter area is increased, while the base contact area is decreased, leading to a significant increase in the ratio of emitter area to base area.
While the lattice design of FIG. 4 increases the emitter surface area, it still suffers from at least one important disadvantage. The drawback of this design is that the emitter regions now contain sections 240, formed at the intersection of the horizontal and vertical portions of the emitter, which do not face a base contact. These sections are referred to as "starved regions" and are indicated by asterisks "* ") on FIG. 4. As starved regions 240 do not face a base contact, the resistance along a current path between these regions and a base contact is larger than for other regions of emitter 208. This is because the resistance of the base region underneath an emitter is orders of magnitude larger than that of the bulk base. Thus, a current flowing between a base contact and a starved region of the emitter encounters much higher resistance than one flowing between a base contact and other regions of the emitter.
The higher resistance attenuates the drive these regions receive from the base voltage applied to the base-to-emitter input of the transistor. This significantly alters the device's current driving capability, because the current emitted by an emitter-base junction is an exponential function of the voltage across the junction. For example, a relatively minor 18 mv reduction, amounting to only 0.3 percent of the applied voltage, can reduce emitter activity by a factor of two. An additional effect of the higher resistance along current paths between the base contact and starved regions of the emitter is that the "average" base resistance for a random current path is increased. This produces an increase in the thermal noise generated during the operation of the transistor as a result of the base resistance.
The existence of starved regions 240 means that not all of the emitter operates with 100 per cent efficiency. Thus, although a lattice design packs a greater amount of emitter surface area into a given base area, the design produces an emitter which is not as fully excited over its entire extent as is an emitter in the conventional design. Although the overall result may be an improvement over the conventional design, it is apparent that it is not optimal. The down component of the total collector resistance has been decreased, but at the cost of impacting the degree of activity of the added emitter regions and the resistance across the input.
What is desired is a design for a multiple emitter bipolar transistor which reduces the total collector resistance while avoiding the disadvantages of the lattice or other common architectures.